General-purpose digital signal processors (DSPs) are used in low cost/low power applications, for example, in modems. Such modems implement more than a single protocol and as such employ software processes to implement these protocols on a programmable DSP. There is a trend in industry to move more of the processing in modem applications into the digital domain from the analog domain. This trend involves doing much of the signal processing in software on a general-purpose DSP core. The advantages of this approach are reduced size and cost resulting from increased levels of integration. Such integration minimizes the number of passive components and increases the number of protocols that can be implemented in a single implementation. However, the power consumption of the programmable DSP core dominates the power consumption of the modem and, therefore, becomes a critical design issue, especially for battery operated portable applications.
DSPs typically spend much of their operating cycles performing multiply-accumulate (MAC) operations to implement filters and these operations dominate the power consumption. The protocols being implemented are always defined in terms of a worst-case operating environment. This includes a worst-case model of the communication channel including worst-case interference, temperature, echo, etc. A model of this environment is used to determine the amount of digital signal processing that is needed to realize a required bit-error-rate for the modem being implemented. Any modem implementation must provide at least this level of performance.
It is well known that much of the DSP complexity in a modem, i.e., the operations that require the most machine cycles to implement, is in implementing the filters in the modem receiver for channel equalization and echo cancellation. The specifications of these filters, for example, A/D precision, number of taps, precision of taps, update algorithm, adaptation rate, etc., are set by the characteristics of the worst-case model of the channel.
Some studies have suggested that the specifications of the filters in hardware implementations can be relaxed in non-worst-case operating environments. For example, U.S. Pat. No. 5,777,914 to C. J. Nicol et al. discloses a hardware arrangement that monitors the signal to noise performance of an adaptive filter over a period of time to yield an average error value. This average error value is used to "scale-back" the precision of the filter tap coefficients in an adaptive manner that, in turn, reduces the power consumption in the filter because the filter response is represented with fewer bits. The signal to noise performance of the filter is reflected in the error used to update the filter coefficients. If the error is very small, the update rate can be reduced without impacting the receiver performance. See an article by C. J. Nicol et al. entitled "A low power 128-tap digital adaptive equalizer for broadband modems", IEEE Journal of Solid State Circuits, Vol. 32, No. 11, November 1997, pp. 1777-1789. Furthermore, the number of taps in the filter can be reduced to reduce the number of multiplications required for equalization. See an article by J. T. Ludwig et al. entitled "Low power filtering using approximate processing for DSP applications", IEEE 1995 Custom Integrated Circuits Conference, pp. 185-188. Although these techniques have been used for filter implementations in hardware, it has historically made little or no sense to use them in software modem implementations because the programmable DSP operates at a fixed frequency and provides adequate performance to implement the worst-case protocol. Indeed, in hardware implementations, the objective of these adaptive techniques is to minimize switching capacitance to reduce power.